1. Field
Example embodiments relate to a storage device, for example, to a device and a method for manufacturing a non-volatile and electrically erasable semiconductor memory device, for example, a flash memory.
2. Description of the Related Art
Non-volatile memory retains information stored in its memory cells even when no power is supplied. Examples include mask ROM, EPROM, and EEPROM.
Non-volatile memory is widely used in various kind of electronic products, for example, personal computers, personal digital assistants (PDAs), cellular phones, digital still cameras, digital video cameras, video game players, memory cards, and other electronic devices.
Memory cards types may include multimedia cards (MMC), secure digital (SD) cards, compact flash cards, memory sticks, smart media cards, and extreme digital (xD) picture cards.
Among non-volatile memory devices, a flash memory is widely used. Flash memory may be divided into a Not-OR(NOR) type and a Not-AND (NAND) type based on a connection structure of cells and bit lines. Because a read speed is faster and a write operation is slower, a NOR-type flash memory may be used as a code memory. Because a write speed is faster and a price per unit area is lower, a NAND-type flash memory may be used as a mass storage device.
NOR-type flash memory may be used in BIOS/networking in a PC, a router, or a hub or in a telecommunications switcher. NOR-type flash memory may also be used to store code or data for cellular phones, personal digital assistants (PDAs), POS, or PCA.
NAND-type flash memory may be used in memory cards for mobile computers, digital cameras, both still and moving, near-CD quality voice and audio recorders, rugged and reliable storage, for example, solid-state disks.
The programming method for NOR-type flash memory is hot carrier injection and the programming method for NAND-type flash memory is Fowler-Nordheim (FN) tunneling.
Advances in consumer electronics cause demand for higher density memory devices. Efforts to manufacture devices meeting this demand often involve scaling down the sizes of gate structures and reducing or minimizing the space between adjacent gate structures.
With the reduction in channel length of transistors, the influence of a source and drain upon an electric field or potential in the channel region may increase. This is referred to as the ‘short channel effect’.
The short channel effect may become especially serious as the gate length of transistors approaches several tens of nanometers. In these cases, variations in threshold voltages may result.
To overcome the short channel effect, halo junction structures has been proposed. However, this approach may reduce on-current and/or increasing leakage current.
Therefore, the halo junction structure may not be suitable for handling short channel effect in sub-nano scaled NAND flash memory devices.
As mentioned above, another related problem is leakage current, for example, trap-assisted leakage current. As shown in FIG. 41, in a conventional charge trap memory device 10, including a substrate 12, a tunnel insulating pattern 14, a charge storage pattern 16, a blocking insulating pattern 18, and a conductive pattern 20, electrons e− may leak from the charge storage pattern 16 through blocking insulating pattern 18 to the conductive pattern 20, for example, as a result of one or more defects D in the blocking insulating layer.
Conventional art publications have studied the characteristics of non-overlapped MOSFETs, and reported that performance degradation was suppressed by using a short non-overlap distance, for example, less than 10 nm. These results indicate that a non-overlapped structure is practically applicable.
Referring now to a conventional device from U.S. patent application Ser. No. 11/643,022, filed on Nov. 20, 2006, the entire contents of which are hereby incorporated by reference in their entirety, shown in FIG. 42, a memory may include a substrate 10, a channel region 40cC, a fringing field 90, an inversion layer 410, and an inversion layer at a source/drain region 430. As shown, a pass voltage of 5 V may be applied to memory transistors MTN−1 and MTn+1, and a select voltage Vsel may be applied to memory transistors MTn. The fringing field 90 from the cell gate potential may cause source/drain inversion, which enables the channel region to conduct a charge.